High Level Synthesis of ASICs under Timing and Synchronization Constraints J. Koerting 4Virtual [¿]

4Virtual [¿]

2015 erbaten bereits 476

Die daraus gewonnenen Ergebnisse werden für eine breit angelegte empirische Studie an einer Auswahl von DAX-Werten zwischen 1960 und 2008 verwendet

muß den Aufbau begleiten

wenn die Persönlichkeitsstruktur

High Level Synthesis of ASICs under Timing and Synchronization Constraints J. Koerting 4Virtual [¿]Computer aided synthesis of digital circuits from behavioral level specifications offers an effective means to deal with increasing complexity of digital hardware design. High Level Synthesis of ASICs Under Timing and Synchronization Constraints addresses both theoretical and practical aspects in the design of a high level synthesis system that transforms a behavioral level description of hardware to a synchronous logic level implementation consisting